This invention relates generally to transistor switching circuitry and more particularly to transistor logic switching circuitry.
As is known in the art, transistor logic switching circuitry is used extensively, as, for example, in memory circuits and selector/multiplexer circuits. In one class of such circuits it is sometimes desired to couple one of the plurality of logic signals to an output selectively in accordance with control signals. For example, in a read only memory application wherein a matrix of fusible links is programmed in a predetermined manner, it is generally desired to detect whether or not a selected one or ones of such fusible links has been programmed in a particular state, that is, blown or not blown. Here the rows of fusible links are coupled to a selector which, in response to the control signals, couples one of the rows to the output. In many circuits of such type the selector includes a plurality of transistors, each one thereof having an emitter electrode coupled to a corresponding one of the columns of the matrix. The collector electrodes of such transistors are connected together at a common terminal, such terminal being coupled to a voltage source through a pullup or load resistor. A diode matrix is coupled to the base electrodes of the plurality of transistors and, in response to the control signals, enables the selection of one of such transistors to couple the column of the matrix of fusible links to the load or pullup resistor. The voltage produced at the common terminal depends upon the programmed state of the fusible link. When such circuit is designed using transistor-transistor-logic (TTL) circuitry, the voltage produced at the common terminal may change typically from between 0.3 volts to +Vcc (i.e., in the order of +5 volts). Because the selector includes a plurality of transistors having common collectors, the capacitance associated with each collector has a cumulative effect on the total capacitance of the circuit. The net result is an increase in the time required for the voltage at the common terminal to swing towards +Vcc, hence increasing the switching time of the memory. One technique used to reduce the switching time has been to limit or clamp the voltage at the common terminal as it goes towards ground or +0.3 volts to some intermediate voltage level. While such technique has reduced the switching time in some applications, it has not reduced the switching time sufficiently in many other applications.